1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to diagnostic mechanisms used to perform diagnostic operations upon data processing systems when those data processing systems are subject to power down during diagnostic operations.
2. Description of the Prior Art
It is known to provide diagnostic mechanisms such as serial scan chains and embedded trace mechanisms within integrated circuits so as to assist in the design of such systems. As the systems increase in complexity, and the number of different circuit elements within the systems increases, there is an increased need for effective, easy to use and efficient diagnostic mechanisms so that the various operational modes of such complicated system-on-chip type designs can be properly evaluated.
It is also known to provide data processing systems with mechanisms whereby portions of the circuit may be placed into low-power states during operation when the capabilities of those portions are not required; this advantageously reduces power consumption. These power control mechanisms are useful in extending battery life within portable systems and it is also generally desirable to reduce power consumption in non-portable systems. With the increasing complexity of integrated circuit designs it is also known that different portions of an integrated circuit may be powered up and powered down during operation depending upon the particular state of the system at that time and the demands being placed upon it. Such integrated circuits execute at significantly higher clock speeds than do the diagnostic mechanisms associated with them. Thus, whilst the diagnostic mechanisms may operate in real time to perform diagnostic operations upon the systems, they are not able to properly track power up and power down events which can take place too rapidly for the relatively slow diagnostic mechanisms.